Work Experience

Principal Design Engineer

Silicon Technology Solutions

September

2013 - December 2013
Design Verification 4 Lane PCIe v1 Block. RTL Implementation of Diamon Search / Heaxagon Based Search Algorithms for FAST Block Motion Estimation. (Xilinx Virtex-4 FPGA). RTL Design Verification using UVM and Synopsys VCS Tools. Design Verification using Modelsim.

Principal Design Engineer

Open-Silicon

September

2012 - August 2013
ASIC Design / Synthesis using Synopsys Design Compiler for TSMC 28nm / 45nm Technology Node Established ASIC Physical Synthesis flow using Synopsys Design Compiler Topographical+SPG at Open Silicon Pakistan Pvt. Ltd ASIC STA / Power Analysis using Synopsys Design Compiler. ASIC Multi-Vt Synthesis for Power / Performance Tradeoff.

Design Engineer

RWR Pvt. Ltd

August

2010 - August 2012
RTL Design for Xilinx FPGAs PCB Design Prototype Testing and Bring-UP.

Education

Portland State University

MS, ECE

2007 - 2009

Graduate Assistant: IC Design and Test Lab

Ghullam Ishaq Khan Institute of Engineering Sciences and Technology

BS, EE

2002 - 2006